Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator

Simulation is the most viable solution for the functional verification of SoC. The acceleration of simulation with multi-FPGA is a promising method to comply with the increasing complexity and large gate capacity of SoC. The most time-consuming factor of multi-FPGA simulation accelerator is signal transfer time between simulator and multi-FPGA system. This paper proposes a performance driven design mapping algorithm for multi-FPGA systems with timemultiplexed interconnection in a simulation accelerator. The proposed design mapping algorithm considering signal probability, net dependency reduction and efficient net clustering shows inter-FPGA signal transfer time reduction to 8%∼18% of traditional algorithms.